1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device including an internal voltage-down converter which steps down an externally applied supply voltage to generate an internal supply voltage. More particularly, the invention relates to a semiconductor memory device including an internal voltage-down converter.
2. Description of the Background Art
Elements in semiconductor integrated circuit devices have been miniaturized more and more as the degree of integration of the devices has increased. As sizes of MOS transistors (insulated gate type field effect transistors) decrease, thicknesses of gate insulating films decrease, and thicknesses of interlayer insulating films between interconnections also decrease. Therefore, if an external supply voltage of a conventional value of, e.g., 5 V were used as an operation supply voltage, disadvantage such as dielectric breakdown would be caused, and thus reliability of the integrated circuit device would be impaired. Therefore, in the semiconductor integrated circuit device such as a semiconductor memory device which is used in a system operating with the conventional supply voltage value of 5 V, the external supply voltage is stepped down or is subjected to voltage down conversion to generate the internal supply voltage, which in turn is used as the operation supply voltage.
An internal voltage-down converter for generating the internal supply voltage is designed such that the internal supply voltage (internal Vcc) generated by the step-down circuit can maintain a level of a predetermined constant value (V0) even if the external supply voltage (external Vcc) becomes higher than the constant value (V0). The operation for maintaining the internal supply voltage (internal Vcc) at the constant voltage value (V0) is referred to as "internal step-down" or "voltage down conversion".
Such internal voltage-down converters are usually provided in semiconductor memory devices such as DRAMs (dynamic random access memories) and SRAMs (static random access memories). The reason for this is that logic LSIs (large scale integrated circuit devices) such as microprocessors which determine system power supplies have not been highly miniaturized as compared with the semiconductor memory devices, and the voltage of 5 V is still used as the system supply voltages.
The purpose for the step-down is to ensure reliability of the internal circuits of the integrated circuit device and to reduce the current consumption. The power consumption is proportional to the square of the voltage. Therefore, the lower operation supply voltage enables the lower power consumption.
FIG. 18 shows a construction of an internal voltage-down converter in the prior art, which is shown in Nikkei Micro Device (Nikkei BP Corp., February 1990, pp. 117-118, FIGS. 2 and 8).
In FIG. 18, the conventional internal voltage-down converter includes a reference voltage generating circuit 500 for generating a reference voltage V0, and an internal voltage generating circuit 550 for generating an internal supply voltage (internal Vcc) in accordance with the reference voltage V0. The reference voltage generating circuit 500 includes a resistor element 501, which is interposed between an external supply voltage (external Vcc) supply node and an output node 504 and has a relatively large resistance, and diode-connected n-channel MOS transistors 502, . . . 503, which are x in number and are interposed in series between the node 504 and a ground potential Vss. The diode-connected MOS transistors 502, . . . 503 each have a threshold voltage VTH. A voltage of x.multidot.VTH is generated as the reference voltage V0 through the output node 504.
The internal voltage generating circuit 550 includes an n-channel MOS transistor 551 which receives at its gate the reference voltage V0, an n-channel MOS transistor 552 which receives at its gate the internal supply voltage (internal Vcc) on a node 559, a constant current source 555 coupled to one conduction terminal of each of transistors 551 and 552, a p-channel MOS transistor 553 which has one conduction terminal receiving the external supply voltage (external Vcc) and the other conduction terminal connected to a node 557, a p-channel MOS transistor 554 which has one conduction terminal receiving the external supply voltage (external Vcc) and the other conduction terminal connected to a node 556, and a p-channel MOS transistor 558 which is responsive to the potential of the node 557 to transmit the external supply voltage (external Vcc) to the node 559 for generating the internal supply voltage (internal Vcc).
The node 556 is connected to the gates of the transistors 553 and 554. The internal voltage generating circuit 550 feeds back the internal supply voltage (internal Vcc) generated at the node 559 for comparing the same with the reference voltage V0 supplied from the reference voltage generating circuit 500, and controls the p-channel MOS transistor 558 in accordance with the result of comparison for controlling the potential level of the internal supply voltage (internal Vcc).
FIG. 19 is a waveform diagram showing an operation of the internal voltage-down converter shown in FIG. 18. In FIG. 19, ordinate indicates the internal supply voltage (internal Vcc), and abscissa indicates the external supply voltage (external Vcc). The operation of the internal voltage-down converter shown in FIG. 18 will be described below with reference to the operation waveform diagram shown in FIG. 19.
Before the external supply voltage (external Vcc) rises up to the predetermined reference voltage V0, the reference voltage V0 supplied from the reference voltage generating circuit 500 changes in accordance with the external supply voltage (external Vcc). More specifically due to the relationship of V0=x.multidot.VTH, one of the transistors 502, . . . 503 is in the off state, and the node 504 is charged through the resistor 501.
In the internal voltage generating circuit 550, this reference voltage V0 and the internal supply voltage (internal Vcc) of the node 559 are compared with each other. The node 559 receives through the transistor 558 the external supply voltage (external Vcc) supplied through a supply voltage node 10.
When the voltage of the node 559 is higher than the reference voltage V0, the conductance of the transistor 552 is higher than the conductance of the transistor 551, and the potential of the node 556 is lower than the potential of the node 557. The potential of the node 556 is fed back to the gates of the transistors 553 and 554. This further increases the potential of the node 557, and the transistor 558 is turned off.
When the reference voltage V0 is lower than the voltage of the node 559, the potential level of the node 557 is at the low level so that the transistor 558 is in the on state, and the external supply voltage Vcc transmitted to the supply voltage node 10 charges the node 559.
Thus, the internal supply voltage generating circuit 550 has a function of equalizing the reference voltage V0 and the internal supply voltage (internal Vcc) applied to the node 559.
When the external supply voltage (external Vcc) is higher than the reference voltage V0, the reference voltage V0 supplied from the reference voltage generating circuit 500 is at a constant value (x.multidot.VTH). In this condition, therefore, the internal supply voltage (internal Vcc) generated from the node 559 is maintained at the constant reference voltage V0 regardless of the rise of the voltage level of the external supply voltage (external Vcc).
On the other hand, to the semiconductor integrated circuit devices such as DRAMs, it is necessary to carry out an acceleration test (i.e., aging test) for screening initial failure caused, e.g., by a particle. In the acceleration test, the semiconductor integrated circuit device is operated under the high-voltage and high-temperature conditions to reveal potential failure for removing the initial failure.
For this acceleration test (aging test), a high voltage must be applied to the internal circuits of an integrated circuit device. However, if the internal voltage-down converter described above is used, the internal supply voltage could not exceed the predetermined voltage V0, so that the aging test of the internal circuits will be impossible. For this reason, various constructions have been proposed for carrying out the aging test of the semiconductor integrated circuit device provided with such internal voltage-down converter.
FIGS. 20-22 show proposed approaches for carrying out the aging test, which are shown, for example, in Nikkei Microdevice, October 1991, pp. 48-52. In each of FIGS. 20-22, ordinate indicates the internal supply voltage (internal Vcc) and abscissa indicates the external supply voltage (external Vcc).
The approaches for carrying out the aging test shown in FIGS. 20-22 will be described below.
In the approach shown in FIG. 20, when the external supply voltage (external Vcc) reaches the predetermined voltage value of V0, the internal supply voltage (internal Vcc) is maintained at the constant voltage value of V0 through the clamp function of the internal voltage-down converter. When the external supply voltage (external Vcc) exceeds a certain voltage V1, the aging mode for carrying out the aging test starts. In this aging mode, the internal supply voltage (internal Vcc) rises in accordance with the rise of the external supply voltage (external Vcc), while keeping a voltage ratio of V0/V1.
In the approach shown in FIG. 21, the aging mode for carrying out the aging test starts when the external supply voltage (external Vcc) reaches the predetermined voltage V1. In the aging mode, the internal supply voltage (internal Vcc) equals the external supply voltage (external Vcc). This approach is realized, for example, by applying the external supply voltage to the internal circuits in the aging mode without passing the same through the internal voltage-down converter.
In the approach shown in FIG. 22, the aging mode starts when the external supply voltage (external Vcc) exceeds the predetermined voltage V1. In the aging mode, the internal supply voltage (internal Vcc) changes in accordance with the external supply voltage (external Vcc) while maintaining the internal voltage at a level lower than the external supply voltage (external Vcc) by a voltage of (V1-V0).
The approaches for carrying out the aging test shown in FIGS. 20-22 have following common features. Before the external supply voltage (external Vcc) reaches the reference voltage V0, the internal supply voltage (internal Vcc) rises with the rise of the external supply voltage (external Vcc). When the external supply voltage (external Vcc) reaches the reference voltage V0, the constant internal supply voltage of the reference voltage V0 is generated due to the clamp function of the internal voltage-down converter. When the external supply voltage (external Vcc) further rises to or above the voltage V1, the aging mode starts, and the internal supply voltage (internal Vcc) rises in accordance with the external supply voltage (external Vcc). The aging test is carried out in accordance with thus risen internal supply voltage (internal Vcc)
As described above, the semiconductor integrated circuit device having the conventional internal voltage-down converter enters the aging mode when the external supply voltage (external Vcc) equals or exceeds the predetermined value.
A screening test is applied to the semiconductor integrated circuit devices before marketing of products for removing defective devices which in turn do not satisfy specification values required to the devices. A certain tolerance of, e.g., 10% with respect to the supply voltage used in a normal operation is permitted for the specification value of the external supply voltage. The screening test uses the supply voltage higher than the permitted maximum value, taking an operating margin into account.
Therefore, if such a high external supply voltage is used in the screening test or the like, the semiconductor integrated circuit device would automatically enter the aging mode. In this case, an unnecessarily high voltage would be applied to the internal circuits, so that stress would generate, and thus the screening test would deteriorate the reliability of the products or devices.